In a variety of applications, including high speed Analog-to-Digital Converters, there exists a need for a high speed near unity gain amplifier (buffer) which has high input impedance (typically at or above about 10.sup.6 ohms), relatively low output impedance (typically about 10.sup.3 ohms or less), and relatively fast response time (typically 10 nanoseconds seconds or less) and relatively low offset voltage (typically 5 millivolts or less).
One prior art buffer circuit consists of the series combination of two n-channel depletion mode transistors with the drain of the first transistor connected to a positive voltage source, the source of the first transistor connected to the drain of the second transistor and to a buffer output terminal, and with the gate and source of the second transistor connected to a negative voltage source. The gate of the first transistor serves as the buffer input terminal. The second transistor serves as an essentially constant current source. The gate-to-drain voltage of each of the transistors varies as the potential level of an input signal varies. This results in the gain of the buffer being typically below 0.95 (with a transistor channel length of about 2 microns or less) which is not acceptable in some applications.
Another circuit useful as a buffer is an operational amplifier with the output connected to the negative input terminal and with the positive input terminal serving as the buffer input terminal. The output of the amplifier serves as the buffer output terminal. Delay around the loop of the amplifier can cause ringing and a relatively low bandwidth resulting in poor response to high frequency signals.
It is desirable to have a buffer circuit which has relatively high input impedance, relatively low output impedance, near unity gain, relatively fast response time and which can be fabricated using metal-oxide-silicon (MOS) transistors formed in the silicon of a silicon-on-sapphire substrate or in bulk silicon.